1. IE browser is NOT supported anymore. Please use Chrome, Firefox or Edge instead.
2. If you are a new user, please register to get an IHEP SSO account through https://login.ihep.ac.cn/registlight.jsp Any questions, please email us at helpdesk@ihep.ac.cn or call 88236855.
3. If you need to create a conference in the "Conferences, Workshops and Events" zone, please email us at helpdesk@ihep.ac.cn.
4. The max file size allowed for upload is 100 Mb.
21–26 May 2017
Beijing International Convention Center
Asia/Shanghai timezone

Design of the FPGA-based Gigabit Serial Link for PandaX-III Experiment

Not scheduled
15m
Beijing International Convention Center

Beijing International Convention Center

No.8 Beichen Dong Road, Chaoyang District, Beijing P. R. China 100101
Poster Front-end electronics and fast data transmission

Speaker

Mr CHENG Li (University of Science and Technology of China)

Description

PandaX-III (Particle And Astrophysical Xenon Experiment III) is aimed to search for NLDBD (Neutrinoless Double Beta Decay) of 136Xe at China Jin Ping underground Laboratory (CJPL). For first phase of this experiment, a high pressure gas Time Projection Chamber (TPC) containing 200 kg, 90% 136Xe enriched gas at 10 bar operates as detector. In the current baseline design, each TCP end-plate composes of 41 Microbulk Micromegas detectors, each read out in 64 X and 64 Y strips, the total number of channels whole TPC is 10496. Readout electronics for this experiment must provide low noise, high energy resolution, capability to process tens of thousands of channels and transfer their effective data, and low level of radioactivity. In order to satisfy the requirement of high data throughput and low radioactivity, we use optical fiber links to communicate between front-end board and back-end board. Front-end board installed inside the water-proof vessel integrates charge of micromegas signals, digitize the waveform and send the data packet to back-end Data Acquisition (DAQ) board. Front-end board needs synchronous information (global clock, global trigger, global reset, etc.), as well as command messages from DAQ board. To accommodate the various types of signals, we propose a user-defined protocol with optical links. Communication of serial transmission is performed using Xilinx FPGA based Gigabit Transceiver (GTP and GTX) with a 1 Gbit/s point-to-point speed. The FPGA on DAQ board also processes event data and realizes 1 Gbit/s Ethernet interface to control PC. Finally, preliminary joint test with detectors is conducted in Shanghai, shows this system good performance and sufficient data bandwidth.

Primary author

Mr CHENG Li (University of Science and Technology of China)

Co-authors

Dr Changqing Feng (中国科学技术大学) Prof. Qi An (University of Science & Technology of China) Prof. Shubin Liu (University of Science & Technology of China)

Presentation materials

There are no materials yet.