1. If you are a new user, please register to get an Indico account through https://login.ihep.ac.cn/registIndico.jsp. Any questions, please email us at helpdesk@ihep.ac.cn or call 88236855.
2. The name of any uploaded file should be in English or plus numbers, not containing any Chinese or special characters.
3. If you need to create a conference in the "Conferences, Workshops and Events" zone, please email us at helpdesk@ihep.ac.cn.
21-26 May 2017
Beijing International Convention Center
Asia/Shanghai timezone
Home > Timetable > Session details > Contribution details

Contribution oral

Beijing International Convention Center - Room 305A

The Semi-Digital Hadronic Calorimeter for Future Leptonic Collider experiments

Speakers

  • imad LAKTINEH

Primary authors

Content

The successful running of the technological prototype of the Semi-Digital Hadronic CALorimter (SDHCAL) proposed to equip the future ILD detector of the ILC has provided excellent results in terms of energy linearity and resolution and also tracking capabilities. Stability with time of the prototype is also successfully tested. To validate completely the SDHCAL option for ILD, a new R&D activities have started. The aim of such activities is to demonstrate the ability to build large detectors (> 2m2). The construction of efficient detectors of such a size necessitates additional efforts to ensure the homogeneity and the efficiency of these large detectors. An important aspect of the new activities is to use a new version of the HARDROC ASIC. The new version has several advantages with respect to the one used in the SDHCAL prototype such as the zero suppression and the I2C protocol. Another development is the DAQ electronic board. A new one is proposed. In addition to a reduced size to cope with the ILD requirements, new features are being implemented. A TCP/IP protocol is adopted in the new card to ensure the coherency of the data transmission. The TTC protocol is also to be used to distribute the clock to the different ASIC on the electronic board. The new DAQ board is being conceived to have the capability to address up to 432 ASICs of 64 channels each. Designs for both the DAQ board and the electronic boards are being finalized and the first boards will be produced soon while 600 of the new HARDROC were produced and tested. A new cassette, to host the active layer while being as before a part of the absorber, is being also conceived. The challenge is to maintain a good rigidity to ensure the perfect contact between the electronic board and the GRPC and also to facilitate the dissipation of the ASIC heating. Finally, the mechanical structure of the new prototype will use a new welding technique to reduce the dead zones and provide less deformed structure. Few attempts using the electron beam welding technique to build small setup have been realized at CERN.