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1. Zhang Ying reported the progress of the pixel analog design. The schematic of the pixel analog was almost ready and similar as ALPIDE and the design in MOST1. The bias current vs the timing response were studied considering the bunch crossing freq of 25ns. When bias current is 440nA, the peaking time of the 400e input charge (~MIP) is about 150ns, while the power density of the analog part only is 138mW/cm2. This was already larger than what was expected in MOST1, although during that time, 25ns BX was not considered.
We need to make sure asap if this power density is acceptable, what is the acceptable value now?
2. Tianya Wu reported the progress of the pixel digital design. The digital pixel was almost ready too and can be simulated. the address decoder was implemented for 32 rows now and in a similar style as in MOST1.
The area of the pixel digital was almost the same too, so currently the layout can be based on the standard cell. We will see if the digital cell has to be further shrunk by customized design.
The next step is to think about the address decoder for 512 rows. It may need higher level of grouping topology. May refer to the MOST1 design.
More designs for the digital part are:
pixel mask bit to mask the noisy pixel. Maybe can be implemented by 1-bit shift registered chain for each pixel.
Test feature for the digital part. For example an external digital pulse injection possibility.
3. The next step for the chip design is to begin the pixel analog+digital integration simulation. That is an (almost final) schematic of the pixel cell will be cross checked, by Zhang Ying(pixel analog designer), Tianya (pixel digital designer), and Weiguo(cross check reviewer).
4. PLL design should also start for the first version of tapeout.
5. Zhang Ying proposed a question on the possible negative high voltage supply. The critical point is how to implemented the IO for this negative high voltage( possible to be ~-6V), and what is the ESD consideration. May refer to similar design.