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MOST2 chip design meeting

Asia/Shanghai

 1. progress of the digital cell design was reported. The address encoder is similar like the design in ALPIDE based on the AERD scheme. This style seems to be welcome by both digital cell design and periphery design, so currently we will continue on this architecture. 

     Delay of the encoder was estimated. Although there were some mismatch of the simulation results and the results given in the reference, it seems that a delay of 20ns is acceptable and achievable. Tianya will continue the design for this spec, and it should be the worst case result (@ss corner, 50 degree, 1.6V VDD ); Xiaomin accepted this spec and design shall based on this condition.

  2. a data compression scheme was discussed, based on the pixel hit pattern. Considering that the design and simulation was not fully done, we agreed with some design constraints of this part: The compression and uncompression scheme should be lossless, and the time stamp should not be mixed; The compression scheme should be able to be turned-off and bypassed, and in this case it should not have any compact on the original data. Since this part is more a new scheme, the full chip simulation will not involve the verification of this part, while the designer herself should make sure the correctness by simulation.

  3. The requirement proposed from the periphery logic was discussed.

     i.there seemed to be no obvious against for the 12 depth of FIFO for each column so far. Further consideration and calculation may needed.

     ii. We were sure that 500ns dead time is the maximum acceptable value, as the trigger efficiency is 99% in this case.

     iii. We agreed that the ducy cycle of 50% for the clock, and jitter of 200ps is the typical value for the 40MHz clk. The worst case of the ducy cycle should not exceed ±10%, i.e. 40%~60%

     iv. We agreed 20ns delay of the column bus is our design spec.

     v. We agreed current address encoding scheme is AERD-like.

  4. The first simulatable periphery logic will be provided within two weeks. Minimum array may be 32col*8row. Analog pixel will also be provided soon.

There are minutes attached to this event. Show them.
    • 08:00 08:20
      requirement discussion 20m
      Slides
    • 08:20 08:40
      Digital Cell 20m
      Slides
    • 08:40 09:00
      Periphery 20m
      Slides