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1. Tianya reported the test status of Tcpx1 chip. S1 & S2 sectors were scanned by Scurve methods and noise and threshold dispersion were extracted. It seems that the S2 has better performance than S1, and the difference mainly came from the diode layout. However the reason was needed to be understood.
2. Zhang Ying reported the test status of Tcpx2 chip with minus substrate voltage. When the VRESET was biased at -6V, both the threshold and the noise increased. However this was not consistent with the simulation results. More chips were needed to be test.
3. Wang Jia reported the test and debug status of the LDO block. It was doubted that the 2V power supply and 1.8V net had some weak tunnel. It was also doubted that the bandgap reference didn't work normal and lead to the glitches. The power plan of the full size chip needs to be carefully considered.
4. Xiaomin proposed to add some JESD features for the high speed data link. However, considering that the 4Gbps mode was very likely not to be used in the MOST2 ladder electronics design, we finally decided not to add new designs or to make too much change on the design. The interface for the mask and calen bits with FPGA needs to be discussed with the backend people.
5. Xiaoting proposed to lower down the power of the CML driver, or to switch to an LVDS driver, when the chip works in low speed mode. The low power switch is preferred for the ladder design, however the detailed design should be carefully considered.
6. Wei Wei reported that the modification for the pixel digital part from 64 rows to 512 rows was completed. However, more simulation on the IR drop effect of the power supply needs further simulation. It was also proposed if the thick top metal and 7 layers of the metal process are available, it will help for the power network design. We need to confirm this from TJ.