Speaker
Description
With the increasingly demanding requirements of high luminosity collider HL-LHC, High-Voltage CMOS (HV-CMOS) sensors, featured a deep n-well separating the transistors and the depletion region, had great radiation resistance and enhanced hit density processing capabilities, is considered as the technology option for LHCb upstream pixel tracker in LHCb Upgrade II. To reduce power density and incorporate more functionality in the same area, the next generation process of HV-CMOS: 55nm HV-CMOS processing sensor prototype called COFFEE has been designed and tested. In this talk, I will introduce the sensor development progress of COFFEE chips through COFFEE chip test. In COFFEE chip test, charge injection, laser and radioactive sources are used for testing the in-pixel circuit functionality, sensor performance and other functional modules. The test results are almost conformed to design expectations and simulation results.
