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1–6 Nov 2026
Dongguan Exhibition International Hotel
Asia/Shanghai timezone

Design and Implementation of the CSNS-II Timing System

3 Nov 2026, 15:00
5m
Dongguan Exhibition International Hotel

Dongguan Exhibition International Hotel

Speaker

UNKNOWN 朱鹏 (高能所)

Description

The China Spallation Neutron Source Phase II (CSNS-II) imposes stringent requirements on the real-time monitoring and safety of high-intensity proton beams, necessitating microsecond-level response times for the Fast Protection System. This paper presents a high-throughput, ultra-low-latency data acquisition and processing platform designed on the Advanced Telecommunications Computing Architecture (ATCA). To eliminate standard bus protocol overheads, the system utilizes a custom backplane enabling deterministic, point-to-point interaction between interface and core logic boards via high-speed LVDS signaling (250 MHz) and multi-gigabit serial links (up to 10 Gbps).The platform features a heterogeneous dual-FPGA architecture to maximize processing efficiency. A Radio Frequency System-on-Chip (RFSoC) acts as the front-end processor, employing 14-bit, 5 GSPS direct RF sampling to capture the current signals with minimal analog path delay. Concurrently, a Kintex UltraScale (KU060) FPGA serves as the central logic engine, aggregating device status and executing global protection logic through 10 Gbps transceivers. This functional partitioning ensures parallel execution of signal acquisition and complex logic processing without resource contention. Preliminary results demonstrate that the architecture significantly reduces system loop latency, satisfying the strict timing constraints of the CSNS-II Machine Protection System while providing a scalable solution for high-power accelerator diagnostics.

Primary author

UNKNOWN 朱鹏 (高能所)

Presentation materials

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