Speaker
Mr
Di Wang
(KEK)
Description
Standard EPICS integration of MRF VME-EVR timing modules relies on VME CR/CSR space for board discovery, base address assignment, and interrupt setup. To address the issue where certain VME CPUs lack hardware support for CR/CSR access in their PCIe-to-VME bridge, an integration approach was implemented to configure the EVR base address and interrupt over the EVR's onboard UDP interface. A low-level epics interface was also implemented for the CPU's Linux VME driver to handle VME address mapping and data access.
Primary author
Mr
Di Wang
(KEK)
