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May 21 – 26, 2017
Beijing International Convention Center
Asia/Shanghai timezone

Development of ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC

May 24, 2017, 4:30 PM
Room 305A (Beijing International Convention Center)

Room 305A

Beijing International Convention Center

No.8 Beichen Dong Road, Chaoyang District, Beijing P. R. China 100101
oral Calorimeters R1-Calorimeters(4)


Hils Maximilian (Technische Universitaet Dresden)


The LHC high-luminosity upgrade in 2024-2026 requires the associated detectors to operate at luminosities about 5-7 times larger than assumed in their original design. The pile-up is expected to increase to up to 200 events per proton bunch-crossing. To be able to retain interesting physics events even at rather low transverse energy scales, increased trigger rates are foreseen for the ATLAS detector. At the hardware selection stage acceptance rates of 1 MHz are planned, combined with longer latencies up to 60 micro-seconds in order to read out the necessary data from all detector channels. Under these conditions, the current readout of the ATLAS Liquid Argon (LAr) Calorimeters does not provide sufficient buffering and bandwidth capabilities. Furthermore, the expected total radiation doses are beyond the qualification range of the current front-end electronics. For these reasons a replacement of the LAr front-end and back-end readout system is foreseen for all 182,500 readout channels, with the exception of the cold pre-amplifier and summing devices of the hadronic LAr Calorimeter. The new low-power electronics must be able to capture the triangular detector pulses of about 400-600 nano-seconds length with signal currents up to 10 mA and a dynamic range of 16 bit. Different technologies to meet these requirements are under evaluation: A preamplifier in 130nm CMOS technology with two gain stages can cover the desired dynamic range while meeting the required noise levels and non-linearity values. Alternatively, developments of pre-amplifier, shaper as well as ADCs are performed in 65 nm CMOS technology. Due to the lower voltage range, 2-gain and 4-gain designs of the analog part are studied with programmable peaking time to optimize the noise level in presence of signal pile-up. Radiation-hard, 14 bit ADC operating at 40 or 80 MHz are also being studied. Results from performance-simulation of the calorimeter readout system for the different options and results from design studies and first tests of the components will be presented.

Primary author

Hils Maximilian (Technische Universitaet Dresden)

Presentation materials