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May 21 – 26, 2017
Beijing International Convention Center
Asia/Shanghai timezone

A monolithic pixel sensor with fine space-time resolution based on Silicon-on-Insulator technology for the ILC vertex detector

May 25, 2017, 2:36 PM
Room 307 (Beijing International Convention Center)

Room 307

Beijing International Convention Center

No.8 Beichen Dong Road, Chaoyang District, Beijing P. R. China 100101
oral Semiconductor detectors R4-Semiconductor detectors(6)


Shun Ono (KEK)


Silicon-on-insulator (SOI) wafer technology can be used to achieve a monolithic pixel detector, in which both a semiconductor pixel sensor and readout electronics are integrated in the same wafer. We are developing an SOI pixel sensor SOFIST, SOI sensor for Fine measurement of Space and Time, optimized for the vertex detector system of the International Linear Collider (ILC) experiment. This sensor has a pixel size of 20$\times$20 um$^2$ with fine position resolution for identifying the decay veteces of short life-time particles. The pixel circuit stores both the signal charge and timing information of the incident particles. The sensor can separate hit events with recording timing information during bunch-train collisions of the ILC beam. Each pixel has multiple stages of analog memories and time-stamp circuits for accumulating multiple hit events. SOFIST Ver.1, the first prototype sensor chip, was fabricated using 0.2 $\mu$m SOI process of LAPIS Semiconductor. The prototype chip consists of 50$\times$50 pixels and Column-ADC circuits in a chip size of 3x3 mm$^2$. We have designed the pixel circuit for the charge signal read out with a pre-amplifier circuit and 2 analog memories. We measured the sensor position resolution with 120 GeV Proton beam at Fermilab Test Beam Facility in January 2017. We observed the position resolution of 3 $\mu$m, which is required as a pixel sensor for ILC vertex detector. In 2016, we have submitted SOFIST Ver.2, which measures the hit timing information. We are designing SOFIST Ver.3 storing both the signal charge and timing information within a pixel area of 20$\times$20 $\mu$m$^2$. We adopt 3D stacking technology which implements additional circuit layer on the SOI sensor chip. The additional layers are connected electrically by advanced micro-bump technology, which can place bump with the pitch of 5 $\mu$m. In this presentation, we report the status of the development and the evaluation of the SOFIST prototype sensor.

Primary author


Dr Akimasa Isikawa (Tohoku University) Mr Daisuke Sekigawa (University of Tsukuba) Prof. Ikuo Kurachi (KEK) Prof. Kazuhiko Hara (University of Tsukuba) Dr Manabu Togawa (Osaka University) Dr Miho Yamada (KEK) Mr Shun Endo (University of Tsukuba) Mr Teppei Mori (Osaka University) Dr Toru Tsuboyama (KEK, High Energy Accelerator Research Organization) Prof. Yasuo Arai (High Energy Accelerator Research Organization (KEK)) Dr Yoichi Ikegami (KEK)

Presentation materials