1. IE browser is NOT supported anymore. Please use Chrome, Firefox or Edge instead.
2. If you are a new user, please register to get an Indico account through https://login.ihep.ac.cn/registIndico.jsp. Any questions, please email us at helpdesk@ihep.ac.cn or call 88236855.
3. If you need to create a conference in the "Conferences, Workshops and Events" zone, please email us at helpdesk@ihep.ac.cn.
4. The max file size allowed for upload is 50 Mb.
May 21 – 26, 2017
Beijing International Convention Center
Asia/Shanghai timezone

An FPGA-Based Hough Transform Track Finder for the L1 Trigger of the CMS Experiment at the High Luminosity LHC

May 25, 2017, 5:06 PM
Room 305E (Beijing International Convention Center)

Room 305E

Beijing International Convention Center

No.8 Beichen Dong Road, Chaoyang District, Beijing P. R. China 100101
oral Trigger and data acquisition systems R3-Trigger and data acquisition systems(5)


Tom James (I)


A new tracking system is under development for operation in the CMS experiment at the High Luminosity LHC. It includes an outer tracker which will construct stubs, built by correlating clusters in two closely spaced sensor layers for the rejection of hits from low transverse momentum tracks, and transmit them off-detector at 40 MHz. If tracker data is to contribute to keeping the Level-1 trigger rate at around 750 kHz under increased luminosity, a crucial component of the upgrade will be the ability to identify tracks with transverse momentum above 3 GeV/c by building tracks out of stubs. A concept for an FPGA-based track finder using a fully time-multiplexed architecture is presented, where track candidates are identified using a projective binning algorithm based on the Hough Transform, and then refined with a Kalman Filter, fully implemented in FPGA. A hardware system based on the MP7 MicroTCA processing card has been assembled, which demonstrates a realistic slice of the track finder in order to help gauge the performance and requirements for a full system. This talk outlines the system architecture and algorithms employed, highlighting some of the performance and latency results from the hardware demonstrator, and discusses the prospects and performance of the final system.

Primary author

Presentation materials