Speaker
Jinlong Zhang
Description
After the Phase-I upgrade and onward, the Front-End Link eXchange (FELIX)
system will be the interface between the data handling system and the
detector front-end electronics and trigger electronics at the ATLAS
experiment. FELIX will function as a router between custom serial links
and a commodity switch network which will use standard technologies to
communicate with data collecting and processing components. The FELIX
system is being developed by using commercial-off-the-shelf server PC
technology in combination with a FPGA-based PCIe Gen3 I/O card interfacing
to GigaBit Transceiver links and with Timing, Trigger and Control connectivity provided by an FMC-based mezzanine
card. Dedicated firmware for the Xilinx FPGA (Virtex 7 and Kintex
UltraScale) installed on the I/O card alongside an interrupt-driven Linux
kernel driver and user-space software will provide the required
functionality. On the network side, the FELIX unit connects to both
Ethernet-based network and Infiniband. The system architecture of FELIX
will be described and the results of the development program currently in
progress will be presented.
Summary
See attached file
