1. IE browser is NOT supported anymore. Please use Chrome, Firefox or Edge instead.
2. If you are a new user, please register to get an Indico account through https://login.ihep.ac.cn/registIndico.jsp. Any questions, please email us at helpdesk@ihep.ac.cn or call 88236855.
3. If you need to create a conference in the "Conferences, Workshops and Events" zone, please email us at helpdesk@ihep.ac.cn.
4. The max file size allowed for upload is 50 Mb.
May 21 – 26, 2017
Beijing International Convention Center
Asia/Shanghai timezone

A readout ASIC for the LHCb Scintillating Fibre (SciFi) tracker

May 23, 2017, 4:30 PM
18m
Room 305E (Beijing International Convention Center)

Room 305E

Beijing International Convention Center

No.8 Beichen Dong Road, Chaoyang District, Beijing P. R. China 100101
oral Front-end electronics and fast data transmission R3-Front-end electronics and fast data transmission(1)

Speaker

Xiaoxue Han (H)

Description

The LHCb detector will be upgraded during the Long Shutdown 2 (LS2) of the LHC in order to cope with higher instantaneous luminosities and to read out the data at 40MHz using a trigger-less read-out system. The current LHCb main tracking system will be replaced by a single homogenous detector based on scintillating fibres. The detector will be built from 2.5 m long plastic fibres with a diameter of 250um. The scintillation light is recorded with arrays of state-of-the-art multi-channel silicon photomultipliers (SiPMs). Each SIPM sensor provides 128 channels grouped in two silicon dies and packaged together. The electrical SiPM signals are collected and processed by the low Power ASIC for the sCIntillating FIbres traCker (PACIFIC). The 64 channel ASIC comprises for every channel analog processing, digitization, slow control and digital output at a rate of 40MHz. The analog processing includes preamplifier, shaping and integration. The integrator is formed by an interleaved double gated integrator and a track and hold to avoid dead time (one integrator is in reset while the other collects the signal). The output of the integrator is digitized using 3 comparators (non-linear flash ADC). The three bits output is then encoded into two bits and serialized to be transmitted to a readout FPGA used for clustering and data-compression. Some auxiliary blocks are also needed to produce a fully functional device and include voltage references, current references, control DACs, power on reset (POR) circuitry and serializers. PACIFIC has been designed using deep sub-micron technologies and actual implementation uses TSMC130nm process. PACIFICr3 was the first full size prototype providing real measurements of signals from 64 channels and including the analog processing, digital control and serialization. PACIFICr4 corrects some issues found in the r3-prototype and updates some parameters to improve signal collection from the detector. The talk will present the ASIC design concept and provide results from laboratory tests and test-beam measurements. These studies include the characterization of prototypes, measurements with electrical signal and light injection and measurement with a radioactive source (Sr90) using full fibre modules. The test-beam results are in particular important to understand the expected physics performance of the full chain from the fibre to the digital PACIFIC output.

Primary author

Presentation materials