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21-26 May 2017
Beijing International Convention Center
Asia/Shanghai timezone
Home > Timetable > Session details > Contribution details

Contribution oral

Beijing International Convention Center - Room 307
Semiconductor detectors

Analysis and simulation of HV-CMOS assemblies for the CLIC vertex detector

Speakers

  • Mr. Matthew BUCKLAND

Primary authors

Content

The requirement of precision physics and the environment found in the proposed future high-energy linear e+e- collider CLIC, result in challenging constraints for the vertex detector. In order to reach the performance goals, various sensor technologies are under consideration. Prototypes of an active pixel sensor with 25 μm pitch (CCPDv3) have been fabricated in a commercial 180 nm High-Voltage CMOS technology. The sensors are capacitively coupled to CLICpix readout ASICs with matching footprint, implemented in a commercial 65 nm CMOS process. Tests of the assemblies were carried out at the CERN SPS using 120 GeV pions over an angular range of 0°-80°. The measurements have shown an excellent tracking performance with an efficiency of >99% and a resolution of 5-7 μm over the angular range. These were then compared to simulations carried out using TCAD, showing a good agreement for the current-voltage, breakdown and charge collection properties. The simulations have also been used to optimise features for future sensor design.