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1. Tianya report about digital design of the pixel
*Tianya reporte Load_C and Load_M in each pixel share the same masking setting (data_IN).
*Xiaomei agreed to connect Load_C and Load_M (1024 channels) to IO.
*Tianya : Clock is supposed to be used for testing
*Xiaomei: 512 clock signal for 512 column, need to prepare for 512 cycle at beginning.
Suggest to provide 10MHz clock from her side , Tianya will receive clock with 10Mhz/512
*Discussion about the clock driver, Xiaomei will take care the driver from IO to pixel array, and Tianya should take care the driver inside pixel array
*Tianya asked Xiaomei to connect Vpluse and Apluse(after pulse EN) to IO
*Tianya will check with Ying whether we need control Load_M and Load_C for individual channel.
*Xiaomei suggested to use keep the same Load_M and Load_C for all channel, and only change con_DATA to mask different pixel.
2. Liang Zhang reported DAC status.
Ying asked for 4 voltage source, 3 current source.
Liang confirmed that DAC needs a standard current input
Liang commented that INL is accumulated error, the error is about 30mV at 1.6V.
Xiaomei commented that the error is tiny below 1.2V
Weiguo comment that monotonicity and dynamitic range is more important than the error.
Weiguo asked that whether MOST1 use similar DAC design and whether they have this problem of larger error in high voltage.
Liang commented that MOST1 has similar issue, and will check with Ying to what is the range of voltage and current output.
Liang reported there are 15 pads in DAC for now.
Maybe need to check with Ying about the Sequence of pads.
To do: Add more current source and voltage source. SPI need to be modified .
3. Weiguo reported about the potential issue in pixel analog.
Need to check with Ying offline
*Calibration capacity (230 af) is too small ? Can not find small capacity in standard library.
Is that accurate to use parasitic capacitance ?
*It took 1ms charging time for our design. But it is faster ( 100ns) for Alice , why is that ?